ABB PLC/ Machine Control EI803F 3BDH000017R1 Ethernet communication module
Brand ABB color standard application Industrial height 136mm rated current 168mA
Protection Level IP45 Suitable for motor power 225KW Application Site Power Industry Material Code GJR2391500R1220 Power industry HIEE401782R0001 Part Number EI803F
Applicable pipe 2 Whether imported is weighing 3.88 kg can be sold nationwide
ABB PLC/ Machine Control EI803F 3BDH000017R1 Ethernet communication module
The logic structure of frequency shift signal modulation is realized in FPGA. The FPGA chip uses 16MHz clock pulse to obtain the required low frequency and carrier frequency signals under the action of frequency division module. The phase continuous modulation of frequency shift signal is realized on the premise that the frequency accuracy of frequency shift signal is guaranteed by using clock synchronization flip-flop and electronic switch.
Kt is a low-frequency square wave signal, G1t and G2t are carrier-frequency square wave signals, CLK is a 16MHz clock pulse, and CS1 and CS2 are electronic switch enable signals. Low frequency divider, carrier frequency divider 1, carrier frequency divider 2, clock synchronization trigger, inverter, electronic switch and adder are implemented by the FPGA internal logic gate array through the state machine. The frequency division of the low frequency divider and the carrier frequency divider is controlled by the input low and carrier frequency trigger signals, and is preset automatically, so that the signal sending system is suitable for a variety of carrier frequency switching, and the universality of the system is achieved.
The internal logic structure of FPGA is written in VHDL language. Figure 3 shows the program flow chart of VHDL language in the frequency shift signal modulation part.
2 Timing design of frequency shift signal detection
The frequency shift signal is detected by high frequency insertion. The 16MHz standard pulse is inserted into the signal to be measured, a carrier frequency period Tz of the signal to be measured is determined by the counter, and its carrier frequency fz is obtained: where Nz is the number of counting pulses in a carrier frequency period.
In order to calculate the low frequency period in the frequency shift signal to be measured, a large number of carrier frequency period Nz needs to be stored. The timer of CPU is used to form an Nz array within a certain time (0.2S), find the switching points of the upper and lower frequencies of the frequency shift signal, and determine the low frequency period by calculating the number of carrier frequency cycles between two adjacent switching points.
Where Nd is the number of frequency cycles between two adjacent upper and lower frequency switching points.
In this paper, the dual CPU completes the precision judgment and timer control of detecting count data independently. The counter part is realized in FPGA, and the principle diagram of frequency shift signal detection is shown.
Experimental result
On the basis of debugging the prototype, the new frequency shift signal sending system is tested experimentally. Among them, 8 kinds of carrier-frequency signals are selected, and the center frequencies are 550, 650, 750 and 850Hz, respectively, and the frequency offset is 55Hz. Eight kinds of low frequency information were randomly selected from the national railway frequency shift signal standard, which were 7, 8, 9, 9.5, 16.5, 17.5, 18.5 and 26Hz respectively.
In order to detect the actual transmitted frequency shift signal, the HP3563A (ControlSystemsAnalyzer) control system analyzer is used to simulate the universal frequency shift signal receiver for spectrum analysis. With a sampling frequency of 2048 points /s and a Hanning window for FFT transformation, the signal spectrum diagram as shown in Figure 6 can be obtained.
ABB PLC/ Machine Control EI803F 3BDH000017R1 Ethernet communication module
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