ABB ICSI16E1 new inventory DCS processor module
Brand ABB color Standard Application Industrial height 315mm rated current 470mA
Protection Level IP45 Suitable for motor power 286KW Application Site Power Industry BOM Number GJR2391500R1220 Power industry HIEE401782R0001 Part number ICSI16E1
Applicable pipe 2 Whether imported is weighing 5.88 kg can be sold nationwide
ABB ICSI16E1 new inventory DCS processor module
MB86S02 video image sensor collects video image information under the control of FPGA. MB86S02 starts video signal acquisition after receiving the acquisition command from PC. FPGA, as the core control unit of the system, is not only responsible for video image acquisition. It is also responsible for the pre-processing of video image information and the data interaction between each unit module of the system. In view of the large amount of video image data, in order to ensure the real-time requirements of the system, the system adopts large-capacity off-chip SDRAMR to cache the collected video image information. The SDRAM controller is implemented by FPGA, and the video image information must be filtered by FPGA after being cached by SDRAM. In order to eliminate the noise interference in the image information, the system uses the median filter to process the collected video information, and the filtered data enters the DSP through the FPGA internal FIFO for the next step of compression processing. After powering on the DSP, the bootstrap program is self-loaded first and waits for the request from FPGA. After receiving the request from FPGA, the DSP establishes an EDMA channel to obtain video data from FPGA. After storing a full frame, the video image is compressed by JPEG and the compressed video image information is cached by FIFO. Under the control of FPGA, the data cache of the USB interface controller is written, waiting for the reading request of the PC, and the USB interface controller writes the data to port 1 of PDIUSBD12 after receiving the reading request of the PC, so that the PC can read the data in the next step.
2 Overall design of system software
The software design of the system can also be divided into two parts according to the overall division of the hardware structure. The operation of the whole system is shown in Figure 2. The programs of FPGA and DSP run independently and complete real-time data interaction through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA, and the DSP establishes an EDMA channel in response to the EDMA request and starts to read the pre-processed data from the FIFO. When the DSP transmits data to the FPGA, it sends an interrupt signal to the FPGA. Let it read the compressed image data out of the FIFO.
ABB ICSI16E1 new inventory DCS processor module
ABB RET650
ABB RK682011-BA
ABB SA801F
ABB SAFT183VMC
ABB SC510
ABB SK616001-A
ABB SNAT602TAC
ABB SNAT603CNT
ABB SNAT604IFS
ABB SNAT609TAI
ABB SNAT634PAC
ABB SPAD346C3
ABB SPBLK01
ABB SPBRC300
ABB SPDSI22
ABB SPHSS13
ABB TK457V050
ABB TP830-1
ABB TPPB-02
ABB TU830V1
ABB UAC318AE
ABB UAD149A0011
ABB UCD224A102
ABB UFC092BE01
ABB UFC718AE01
ABB UNS0119A-P V101
ABB UNS0874A
ABB UNS2980c-ZV4
ABB V4550220-0100
ABB 504994880
ABB 0745648E
