ABB FPX86-9329–C new inventory DCS processor module
Brand ABB color standard Application Industrial height 215mm rated current 470mA
Protection Level IP45 Suitable for motor power 396KW Application Site Power Industry Material Code GJR2391500R1220 Power industry HIEE401782R0001 Part No. FPX86-9329–C
Applicable pipe 2 Whether imported is weighing 4.88 kg can be sold nationwide
ABB FPX86-9329–C new inventory DCS processor module
MB86S02 video image sensor collects video image information under the control of FPGA. MB86S02 starts video signal acquisition after receiving the acquisition command from PC. FPGA, as the core control unit of the system, is not only responsible for video image acquisition. It is also responsible for the pre-processing of video image information and the data interaction between each unit module of the system. In view of the large amount of video image data, in order to ensure the real-time requirements of the system, the system adopts large-capacity off-chip SDRAMR to cache the collected video image information. The SDRAM controller is implemented by FPGA, and the video image information must be filtered by FPGA after being cached by SDRAM. In order to eliminate the noise interference in the image information, the system uses the median filter to process the collected video information, and the filtered data enters the DSP through the FPGA internal FIFO for the next step of compression processing. After powering on the DSP, the bootstrap program is self-loaded first and waits for the request from FPGA. After receiving the request from FPGA, the DSP establishes an EDMA channel to obtain video data from FPGA. After storing a full frame, the video image is compressed by JPEG and the compressed video image information is cached by FIFO. Under the control of FPGA, the data cache of the USB interface controller is written, waiting for the reading request of the PC, and the USB interface controller writes the data to port 1 of PDIUSBD12 after receiving the reading request of the PC, so that the PC can read the data in the next step.
2 Overall design of system software
The software design of the system can also be divided into two parts according to the overall division of the hardware structure. The operation of the whole system is shown in Figure 2. The programs of FPGA and DSP run independently and complete real-time data interaction through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA, and the DSP establishes an EDMA channel in response to the EDMA request and starts to read the pre-processed data from the FIFO. When the DSP transmits data to the FPGA, it sends an interrupt signal to the FPGA. Let it read the compressed image data out of the FIFO.
ABB FPX86-9329–C new inventory DCS processor module
ABB DCP02
ABB DCP10
ABB DDI03
ABB DDO02
ABB DI610
ABB DI620
ABB DI810
ABB DI814
ABB DLM01
ABB DO610
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ABB DPW01
ABB DRA02
ABB DSAI146
ABB DSAO110
ABB DSBB175
ABB DSDP170
ABB DSDX404
ABB DSIH72VP ENOK
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ABB DSPC172
ABB DSPC172H
ABB DSPC406
ABB DSQC202
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ABB DSQC327A
ABB DSQC346G
ABB DSQC346U
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ABB DSQC626
ABB DSQC627 3HAC020466-001
ABB DSTD108
ABB DSU10
ABB DSU14
ABB EHDB130
ABB EHDB280
ABB IMFEC12
ABB IMMFP12
ABB IMMPI01
